This invention relates in general to first-in-first-out (FIFO) circuits, and more particularly, to a FIFO circuit wherein the data storage capacity is easily expandable without imposing design modifications on the preexisting control circuitry and arranged such that the oldest data at the head of the queue is always located in a predetermined register.
First-in-first-out circuits can be found in a myriad of applications in which there is a need to store data for a period of time and later read the same data while preserving the incoming order. One such application is in the field of data communications, for example a modem circuit, wherein a burst of data may be written to the FIFO at a high data rate, possibly from a computer interface clocked at 10 MHz, and read at a much slower data rate for transmission over a conventional communication link operating at say 9600 baud or higher. The temporary storage provided by the FIFO circuit allows the computer interface to dump the burst of data therein and return to performing other processing tasks. The modem circuit may then clock the data out at an convenient lower transmission frequency and interrupt the computer when it is ready for the next data burst.
A conventional FIFO circuit may comprise a predetermined number N of serially coupled registers wherein each register is M-bits wide, M and N being positive integers. An M-bit data word is written to the data input of the FIFO and any existing data is shifted to the next higher position such that the oldest data occupies the highest position that is farthest from the input data bus. A counter is incremented with each M-bit data word added to the FIFO in order to keep track of the highest data position, i.e., the head of the queue, and may be decoded via address logic at any point in time. Typically, there are N address decode circuits, one for each register in the FIFO. During the read cycle, the counter identifies the head of the queue through the address decode logic and the M-bit data word stored therein is read from the decoded position after which the counter is decremented. One of the disadvantages of the aforedescribed conventional FIFO circuit is the requirement to read the counter, decode the address of the highest data position and read the M-bit data word. The process requires multiple clock cycles to perform the series of operations thereby increasing the total data access time. Moreover, the address decoder must have high power drivers which are precharged to provide sufficient drive along the data read lines. The precharging of the data read lines also requires extra clock cycles and slows the performance of the FIFO.
Another distinct disadvantage of the prior art FIFO is the difficulty associated with expanding the length, the value of N. In general, it is necessary to increase the width of all address decode logic as the length of the FIFO increases. For example, if the FIFO control circuitry was originally designed with 8-bits for addressing 256 register locations (N=256) and later a design modification called for additional length of 256 (total 512) in the FIFO, then since each decode circuit is the same width, all 512 address decode circuits including the original 256 must be relayed-out for 9-bits of addressing range to accommodate the increased data storage capacity. Hence, the scheme using address decoding of the highest position is inconvenient, consumes excessive power and inhibits design flexibility especially when attempting to expand the capacity thereof.
Hence, what is needed is an improved FIFO circuit which is expandable without modification in the preexisting control circuit and arranged such that the oldest data position is always at a predetermined register location thereby eliminating the need for the address decoding to find the head of the queue.